This sends the data to the IP components that need it. The high-frequency architecture has a similar set of IP components, including the processor, but uses streaming interfaces to pass data from the ADC interfaces to a new sample store and router IP. This architecture cannot reach very high frequencies, due to the processing time of the ISR in the processor. The standard PWM frequency is 8kHz and the control frequency is 16kHz. The architecture uses multiple instances of a drive subsystem, which makes it straightforward to extend the design to multiple motor-control axes.
Synchro resolver max 10 fpga software#
The user can select which signals to use, and view their output using the console software provided.Įxternal IP for accelerating the DC-DC and field-oriented control (FOC) calculations was created with the Altera DSP Builder Simulink blockset. The processor reads both the sigma-delta and MAX 10 ADC signals. The processor’s interrupt service routine (ISR) reads data from interface IP components, performs control calculations in software or via calls to accelerator IP, and writes outputs to interface IP components, including the DC-DC converter interface and drive subsystem PWM IP.įigure 2: A processor-centric approach to single-FPGA motor control (Source: Altera) An interrupt from the drive subsystem synchronizes the processor control software to the PWM and ADC readings. The processor-centric architecture uses a memory-mapped interface to connect all IP components.
Ability to log data at the control-loop-update frequency of around 100kHz. Ability to view and log data from both types of ADC using PC-based console software. The ability to use and compare external sigma-delta ADCs with the internal successive-approximation ADCs used in the Altera MAX 10 FPGA. There are a number of design requirements to ensure maximum flexibility in the controller: The second uses direct data connections between IP components to remove the processor from the control loops, but retains it for higher-level functions. The first uses the processor to coordinate all functions. We have tried two approaches to high-speed motor control using an FPGA. The FPGA system designs described here build on these reference designs. DC-DC and motor axes controlled by an FPGA development board connected via HSMC connector. MOSFET switching transistors to support 100kHz+ PWM. Support for encoder/resolver/Hall motor-position feedback. Digital signals are provided by sigma-delta analog-digital converters (ADCs) Both analog and digital feedback measurements. Two 3-phase motor drives, or six half-bridge outputs. 12 - 48V DC link generated by bidirectional, 2-phase DC-DC converter. It has also developed a motor-control hardware platform, the Tandem Motion-Power, for academic or commercial research, which includes: This article describes a system architecture and scheduling mechanism for high-frequency control loops and combined motor-control and power conversion in an FPGA.Īltera provides a reference design for a ‘drive-on-a-chip’ FPGA system. SiC and GaN devices currently in development may offer a way forward, with both very low switching and on-resistance losses, reducing the efficiency penalty of switching at high frequencies, as well as higher power capability.īut how are we to control such high-speed systems? One approach would be to program an FPGA to create a system-on-chip including the necessary I/O and processing for multiple functions, for example both power conversion and multi-axis motor control (see Figure 1).įigure 1: An FPGA-based motor control system (Source: Altera) MOSFET switches can switch this fast, but are often unsuitable for high-power applications. The IGBT switches used in many power converters cannot switch quickly or efficiently enough to match pulse-width modulation (PWM) and control-loop-update frequencies that are rising to 100kHz. The increasing use of electric motors spinning at up to 100,000 rpm, in applications ranging from electric turbochargers to surgical instruments, is creating new challenges in the design of control circuits.
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